1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit having a DLL (Delay Locked Loop) circuit and a special power supply circuit for the DLL circuit.
2. Description of the Related Art
Recently, an operation speed of a semiconductor integrated circuit has been increased, and a circuit scale thereof has become large. Further, it has been necessary to supply a synchronized signal (phase synchronized clock signal) to a specific circuit in a large scale semiconductor integrated circuit.
For example, an operation speed of a memory device, e.g., a synchronous DRAM (SDRAM), now exceeds 100 MHz, and a DLL circuit must be used to synchronize a signal with an external clock and supply the synchronized signal to a plurality of output buffers, so as to remove a delay of an internal clock. Namely, a phase of the external clock is coincident with that of the internal clock, and thereby a delay or fluctuation of an access time is removed.
Specifically, in a SDRAM, a DLL circuit must be used to synchronize an internal clock with an external clock and supply the synchronized internal clock to a plurality of output buffers, so as to remove a delay of an internal clock. Namely, a phase of the external clock is coincident with that of the internal clock, and thereby a delay or fluctuation of an access time is removed. Further, in accordance with increasing the operation speed of the semiconductor integrated circuit, the internal clock generated by the DLL circuit should have much higher accuracy.
In a semiconductor integrated circuit of a related art, a DLL circuit and peripheral circuits except for the DLL circuit commonly receive the same power supply voltage output from a power supply circuit. Therefore, when the peripheral circuits use a large current from the power supply circuit or when noise is caused in the power supply voltage in an area of the peripheral circuits, the power supply voltage applied to the DLL circuit is lowered or fluctuated by the noise, and the internal clock output from the DLL circuit is not stable and the accuracy (synchronization with the external clock) of the internal clock is decreased. In addition, the internal clock output from the DLL circuit may include a jitter.
The related arts and their associated problems will be described in detail later with reference to the accompanying drawings.